The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device employing MOSFETs (MOS IC).
As the reduction of the MOSFET channel length is pursued and the intensity of the electric field between its source and the drain becomes high along with the advancement in the high density integration of the MOS IC, the reliability of the IC is reduced due to a hot carrier effect. The hot carrier effect which is especially conspicuous in an N-channel MOSFET is caused by the generation of the electron and hole pairs through collision of carriers (electrons in the N-channel MOSFET) which are accelerated by the electric field with silicon lattices in the vicinity of the drain edge, and the trapping of the electrons moving toward the gate electrode in the gate oxide film. The trapped electrons become the cause which brings about the shift of a threshold of the MOSFET, and a degradation of characteristics such as the reduction of the value of gm.
A MOSFET with lightly doped drain (LDD) structure in which the drain region is constituted of a high concentration impurity diffused layer and a low concentration impurity diffused layer added in a part nearer to the gate electrode, is in widespread use as being effective for relaxation of the hot carrier effect. Since, however, the withstand voltage against punch-through is determined by the distance between the high concentration impurity diffused layer of the drain region and the high concentration impurity diffused layer of the source region (usually it has a constitution similar to that of the drain region) even in the LDD structure, it is difficult to reduce the channel length to below 0.6 .mu.m when the power supply voltage is 5 V.
Moreover, an extremum exists for the bias condition under which the hot electron effect is most likely to occur. For example, in a circuit with a power supply voltage of 5 V, the effect is most likely to occur when the gate voltage is about 2 to 2.5 V. However, among circuits equipped with a plurality of CMOS inverters there exist circuits whose input voltages remain in the aforementioned range of 2 to 2.5 V for a considerable length of time in the process of transition of the signal output due to the demands on the circuit. Examples of such a circuit include an input buffer which receives a signal that is given as a TTL output, for instance, an address inverter in a semiconductor memory. Accordingly, the reliability of such a semiconductor integrated circuit device is dominated by the properties of the N-channel MOSFET of the input buffer.